This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a fuse latch array system for an embedded DRAM (eDRAM) having a micro-cell architecture, a wide data bandwidth and a wide internal bus width.
Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, DRAMs are made of a plurality of blocks or micro-cells. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16xc3x97 to 256xc3x97) than that of a bank of a conventional stand-alone DRAM. Only one block of the eDRAMs is activated each time. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
In order to effectively utilize the large DRAM cache size, a small SRAM unit about the same size of an eDRAM block is used. The SRAM unit serves as a cache interface between an eDRAM and processor(s). The wide internal bus is used for transferring data among eDRAM, SRAM and the processor(s). More specifically, data residing in eDRAM memory cells coupled to a wordline traversing an eDRAM block is transferred to primary sense amplifiers. The data is then transferred to corresponding secondary sense amplifiers. The data is then transferred to the SRAM and stored in the memory cells thereof at the same wordline location. A TAG memory records the block address of the data stored within the SRAM. The data is then transferred to the processor(s).
Generally, neither column addressing nor column decoding is provided for the wide bandwidth eDRAM configuration, since they are not necessary. Hence, a main challenge of the wide bandwidth eDRAM configuration is to provide an effective column redundancy scheme to repair defective column elements without using column addressing. Most of the conventional DRAM approaches require a column address to indicate the location of failed column elements requiring repair.
In a conventional DRAM array, bitline pairs are grouped hierarchically by column address. Only one data bit from a group of bitlines is selected to be transferred via the local and global datalines each time. Therefore, the most common redundancy approach for the conventional DRAM is to provide repair for whole group of bitlines using the column address.
This approach does not lend itself to a wide bandwidth eDRAM, because data from every pair of bitlines of the eDRAM is simultaneously accessed. Further, since all the datalines are coupled to the eDRAM, the data from every pair of bitlines is simultaneously transferred to SRAM; and since all the datalines are coupled to the SRAM, the data from the SRAM is all simultaneously transferred to the processor(s). For such a one-to-one wiring configuration, if any of the datalines fail and no redundancy is offered, the chip must be discarded. If, however, redundancy bitlines are provided in the wide bandwidth eDRAM, it is not easy to correctly replace the failed pair of bitlines without affecting the integrity of the data. Additionally, it is difficult to locate the failed pair of bitlines in the wide bandwidth eDRAM, since, as noted above, column addressing is not available for the wide bandwidth eDRAM.
To overcome the above disadvantages, fuse latch scanning designs have been implemented where, during power-on, all the fuse information, from a fuse bank is scanned into fuse latches or registers, to be used for redundancy replacement. Each fuse latch is typically closely located to the column region for its respective bank. When column address bits are received, a comparison between the incoming address and the stored column address determines whether the DRAM array unit being accessed has to use the redundant elements or not.
The fuse latches are conventional master-slave like shift registers. During power-on, the fuse information containing the failure column address bits are scanned into the shift registers sequentially. The shift registers are decoded (or activated) locally using the corresponding bank addresses. Therefore, in conventional fuse latch array designs, it is preferable that each fuse latch is located in the vicinity of its respective bank.
For a high-performance micro-cell architecture, however, to place fuse latches close to their respective banks is not practical. This is because the size of each bank is very small, and there are a high number of banks. Therefore, a significant area overhead is expected by placing the fuse latches close to their respective banks. It is more practical to localize all the fuse data in a latch array.
Accordingly, a need exists for a fuse latch array system for an eDRAM having a micro-cell architecture, a wide data bandwidth and a wide internal bus width for localizing all the fuse data.
A major aspect of the present invention is to provide a fuse latch array system for an embedded DRAM (eDRAM) having a micro-cell architecture, a wide data bandwidth and a wide internal bus width for localizing all the fuse data.
Accordingly, a fuse latch array system for an eDRAM having a micro-cell architecture, a wide data bandwidth and wide internal bus width is disclosed for localizing all the fuse data for redundancy replacement purposes. The fuse latch array system includes a fuse latch array having a plurality of memory cells where fuse information is scanned therein sequentially or parallel, or a combination thereof to be compatible with conventional fuse latch scanning protocols, during power-on. Each memory cell includes a master register or latch controlled by complementary clock signals and a slave register or latch.
When the fuse information is stored in the fuse latch array, it is accessed as a page during a page mode operation. The accessed page contains column redundancy information corresponding to the active bank. The fuse latch array is decoded by row and column, so that the memory cell corresponding to the active bank can be easily located, even if there are thousands of banks within the eDRAM.
Once the memory cell corresponding to the active bank is located, the column redundancy information is retrieved for use in identifying the defective column of the active bank. The defective column is identified using a redundant decoder. If more than one group of datalines are provided for repair, multiple parallel decoding is utilized to locate multiple defective columns simultaneously and replace them simultaneously during a redundancy operation using a conventional multiplexer circuit. The page mode operation of the fuse latch array system of the present invention ensures the redundancy operation is performed within one clock cycle.